Inter-element isolation techniques of a semiconductor apparatus are roughly divided into the local oxidation of silicon method (hereinafter, referred to as a LOCOS method) and the trench element isolation method.
FIG. 6 is a diagram illustrating a conventional semiconductor apparatus. FIGS. 6(a) and 6(b) are a plane view and a cross-sectional view (X-X line cross-sectional view of FIG. 6(a)) showing transistors isolated by an element isolation region formed by the LOCOS method.
In this semiconductor apparatus 10, adjacent element regions 10a and 10b are isolated by a field oxide film 12 that forms an element isolation region 10c. 
For each of the element regions 10a and 10b, a gate electrode 17 is formed with a gate insulating film 16 interposed therebetween. On both sides of the gate electrode 17, a source region 15a and a drain region 15b are formed.
FIG. 7 is a diagram illustrating a method of manufacturing a conventional semiconductor apparatus using the LOCOS method in the order of the steps (FIGS. 7(a)-7(c)).
First, a thermal oxide film 12a is formed on a silicon substrate, and a nitride film 13 having an opening at a portion to be the element isolation region 10c of the silicon substrate 11 is formed (FIG. 7(a)).
Next, a field thermal oxide film 12 is formed in the element isolation region 10c positioned between the element regions 10a and 10b by thermal oxidation processing, using the nitride film 13 as a mask (FIG. 7(b)).
Subsequently, after the above-described nitride film 13 is removed, the gate insulating film 16 and the gate electrode 17 are formed in the element regions 10a and 10b. Further, the source region 15a and the drain region 15b are formed on both sides of the gate electrode 17.
FIG. 6(c) is a cross-sectional view showing a structure in which element regions are isolated by an element isolation region formed by the trench isolation method, in a conventional semiconductor apparatus, and shows the portion corresponding to the X-X line cross-section of FIG. 6(a).
In this semiconductor apparatus 20, adjacent element regions 20a and 20b are isolated by a trench isolation section that is used as an element isolation region 20c. 
Here, the trench isolation section has a structure in which an isolator 24 is embedded in a trench groove formed on a silicon substrate 21 with a thermal oxide film 22 interposed therebetween. Further, in each of the element regions 20a and 20b, a gate electrode 27 is formed with a gate insulating film 26 interposed therebetween, and a source region 25a and a drain region 25b are formed on both sides of the gate electrode 27.
FIG. 8 is a diagram illustrating a method of manufacturing a conventional semiconductor apparatus using the trench isolation method, in the order of the steps (FIGS. 8(a)-8(d)).
First, a thermal oxide film 28 is formed on the silicon substrate 21, and a nitride film 29 having an opening at a portion that is to be an element isolation region of the silicon substrate 21 is formed (FIG. 8(a)).
Next, the thermal oxide film 28 and the silicon substrate 21 are etched to form a trench groove 21a, with the nitride film 29 as an etching mask (FIG. 8(b)). Subsequently, after a thermal oxide film 22 is formed on the inner surface of the trench groove 21a, a dielectric 24 is embedded in the trench groove 21a to form the element isolation region 20c (FIG. 8(c)). The nitride film 29 is used as an etching stopper upon etching the dielectric 24 formed on the entire surface, in a process of embedding the dielectric 24 in the trench groove 21a. The nitride film 29 is removed after the formation of the trench isolation region 20c. 
Next, after removing the thermal oxide film 28, the gate insulating film 26 and the gate electrode 27 are formed in the element regions 20a and 20b. Furthermore, the source region 25a and the drain region 25b are formed on both sides of the gate electrode 27 (FIG. 8(d)).
The LOCOS method described above is for forming an element isolation region by thermally oxidizing a surface region of a silicon substrate selectively, and the formation processing of an element isolation region is simply a selective thermal oxidation. However, as illustrated in FIG. 9(a), it has a shortcoming in that a bird's beak B is formed on the side section of an element isolation region, and the width of element regions, which are to be a source region and a drain region, cannot be controlled accurately. In FIG. 9(a), the symbol 12 denotes a field oxide film formed on the silicon substrate 11 and symbol 13 denotes a nitride film used as a mask for forming the field oxide film 12.
On the other hand, the trench isolation method is for forming an element isolation region by selectively forming a trench on a surface region of a silicon substrate and filling the inside of the trench with an insulating material such as an oxide. In comparison to the above-described LOCOS method, in the trench isolation method, it is possible to form a small element isolation region with high precision and the trench isolation method is suitable for forming an element isolation region for isolating fine element regions.
By the way, there is a trend of a drastic increase in the number of elements mounted in a semiconductor apparatus in recent years with a shift towards high performance and high function semiconductors. In order to materialize such semiconductors, fine processing techniques are needed, and for processing rules for 0.25 um or less, the trench isolation technique is mainly used.
However, as a problem to be solved for the trench isolation technique, there are cases where, due to a thermal oxidation step for forming a gate isolation film, the thermal oxidation step being performed after the completion of a process of embedding a dielectric in a Si groove (trench groove formed on a silicon substrate), silicon on a sidewall of a trench groove is oxidized, the volume inside the Si groove increases and compression stress is applied to the silicon constituting an active region (element region), thereby a crystal defect of the silicon occurs in the vicinity of a trench groove.
For this reason, an issue such as junction leak was induced at a boundary section between a trench isolation region and an element region (activation region).
Such a crystal defect due to thermal oxidation of silicon at a sidewall of a trench groove occurs in an element region of a low voltage transistor in a semiconductor apparatus in which a large-sized high voltage transistor and a small-sized low voltage transistor are formed on the same silicon substrate.
Such a crystal defect prominently appears especially in a semiconductor apparatus having a high-density pattern, such as SRAM. When the amount of thermal oxidation is great upon forming an oxide film, for example when a gate oxide film for high voltage operation of 5 v-40 v is grown, a serious defect in LSI operation occurs, such as an increase in leak current.
As a method for avoiding such a problem, as shown in FIG. 10(a), a method of forming the nitride film 23 after the oxide film 22 is formed on a side surface of a trench formed on the silicon substrate 21 and then embedding the dielectric 24 in a trench groove is known (for example, see Patent Literature 1).
In this structure, oxidation of a sidewall of a trench groove by thermal oxidation after the formation of the trench groove is prevented by the nitride film 23, and an increase in volume in the trench groove is inhibited.
Further, aside from the issue of the above-described crystal defects, there is also an issue of an oxide film becoming thin at a boundary between a trench isolation groove and an element region (activation region). Such an issue occurs for the following reason: after an insulating film is embedded in a trench groove (FIG. 8(c)) and the oxide film 28 is removed, a stress is applied to the top corner section of the trench groove upon forming a gate oxide film by thermal oxidation of a silicon substrate surface, and due to the effect of this stress, the film thickness of the oxide film formed by thermal oxidation becomes thinner in comparison to regions other than the edge section of an element region or regions other than the edge section of an element isolation region at a boundary between the trench isolation groove and the element region (activation region). For example, a gate insulating film used in a high voltage transistor has a film thickness of 14 nm or greater. However, the film thickness becoming thin at a boundary between a trench isolation groove and an element region (activation region) not only leads to a decrease in breakdown voltage, but also causes a double threshold issue.
FIG. 9(b) is a diagram illustrating such a double threshold issue.
In other words, in a transistor having a normal threshold property, in accordance with an increase in gate voltage Vg, drain current Id smoothly rises from a predetermined gate voltage value as indicated by L1 (solid line) in the graph. In contrast, in a transistor having a double threshold property, in accordance with an increase in gate voltage Vg, drain current Id starts to rise at a gate voltage value that is lower than normal, and after the drain current is in a saturated state for a moment, the drain current starts to rise again in response to an increase in gate voltage, as indicated by L2 (dotted line) in the graph. In such a transistor having a double threshold property, linear control of drive current or the like is impossible.